Products

The FPGA board offers flexible memory configurations supporting over 48 GBytes of memory, sophisticated clocking and timing options, and four front panel QSFP cages, each supporting up to 100 Gbps (4×25) – including 100GbE.

The A10P3S provides a variety of interfaces for high-speed serial I/O as well as debug support. Four QSFP cages are available on the front panel, each supporting 100GbE, 40GbE, or four 10GbE channels. The QSFP SerDes channels are connected directly to the Arria 10 FPGA, thus removing the latency of external PHYs. The QSFP cages can optionally be adapted for SFP+.

Several additional interfaces also support high-speed I/O. Two Gen3 x8 PCIe interfaces connect to the FPGA via 16 SerDes lanes, allowing for a x8 PCIe connection in a standard slot or two x8 interfaces in a bifurcated slot. Two SerDes lanes are available via SATA connectors to connect external storage devices or provide direct board-to-board communication. An Ethernet connector provides a 1000BASE-T connection to the SoC.

A USB 2.0 interface is available for debug and programming support. The USB features a built-in Altera USB-Blaster and is connected to the Board Management Controller. The board also supports timestamping with provision for a 1 PPS and reference clock input.

The A10P3S also incorporates a Board Management Controller (BMC) for advanced system monitoring, which greatly simplifies platform management.

The board offers an extremely flexible memory configuration, with two SODIMM sites that support DDR4 SDRAM, QDR-IV, and QDR-II+. Memory card options include the following: up to 16 GBytes of DDR4 with optional error-correcting codes (ECC), up to 36 MBytes QDR-IV (1 bank x36), and up 72 MBytes QDR-II+ (1 bank x36). Additional on-board memory includes up to 16 GBytes DDR4 and 128 MBytes flash with factory default and support for multiple FPGA images. Boards with the Arria 10 SX also feature a MicroSD connector with a MicroSD memory card that includes the ARM/SoC operating system and filesystem.

FPGA

• Intel Arria® 10 GT/GX/SX FPGA
• ARM Cortex board - Dual-core ARM Cortex-A9 MPCore; up to 1.5 GHz CPU operation per core (SX only)
• High-performance, multi-gigabit SerDes transceivers @ up to 28 (GT) or 17 (GX/SX) Gbps
• Up to 1150 (GX/GT) or 660K (SX) logic elements available
• Up to 53 (GT/GX) or 42 (SX) Mb of embedded memory
• 1.6 Gbps LVDS performance
• Up to 3,376 (SX/GX) or 3,036 (GT)18×19 variable-precision multipliers

On-Board Memory

• One bank of up to 16 GBytes DDR4 (x72 GX/GT, x40 SX)
• 128 MBytes of flash memory for booting FPGA

MicroSD Card

• MicroSD card containing ARM/SoC OS and filesystem (SX only)

Optional SODIMM Memory

• DDR4: x72 w/ECC
  • Up to 16 GBytes per SODIMM

• QDR-IV: 1x bank of x36
  • Up to 36 MBytes per SODIMM

• QDR-II+: 1x bank of x36
  • Up to 72 MBytes per SODIMM

PCIe Interface

• Two x8 Gen1, Gen2, Gen3 interfaces direct to FPGA (One x8 interface in a standard slot; two x8 interfaces requires bifurcated slot)

USB Header

• Micro USB port (USB 2.0) for debug and programming FPGA and Flash
• Built-in Altera USB-Blaster

Timestamp Header

• 1 PPS input
• Reference clock input

QSFP Cages

• 4 QSFP28 (zQSFP) cages on front panel connected directly to FPGA via 16 SerDes (no external PHY)
• Each supports 100GbE (GT only), 40GbE, or 4 10GbE
• Backward compatible with QSFP and can be optionally adapted for use as SFP+

Serial ATA

• Two SATA connectors, connected to FPGA

Ethernet

• RJ-45 Ethernet jack for 1000BASE-T connection to the SoC (SX only)

Board Management Controller

• Voltage, current, temperature monitoring
• Power sequencing and reset
• Field upgrades
• FPGA configuration and control
• Clock configuration
• I2C bus access
• USB 2.0 and JTAG access
• Voltage overrides

Size

• 3/4-length, standard-height PCIe slot card
• 241mm x 111.15mm
• Max. component height: 14.47mm

There are a number of different configurations available. Please contact Sarsen Technology to discuss the options.