Products

Configuration via Protocol (CvP) Supported

• High density Intel Stratix V GX/GS
• PCIe x8 interface supporting Gen1, Gen2, or Gen3
• Four SATA connectors, up to 6 Gbps each
• Timestamping support
• Board Management Controller for Intelligent Platform Management
• Utility I/O includes: USB 2.0, RS-232, and JTAG

• VITA 57 FMC site for I/O with full High Pin Count support

The S5PE-F provides a variety of interfaces for high-speed serial I/O as well as debug support. Four SerDes lanes are available via four SATA connectors to connect external storage devices with the FPGA or provide direct board-to-board communication. The x8 PCIe interface provides 8 SerDes lanes to the Stratix V FPGA. USB 2.0, RS-232, and JTAG interfaces are available for debug and programming support. The board also supports timestamping with provision for a 1 PPS and reference clock input as well as RS-232 for connection to GPS or other time sources.

An optional VITA 57 FMC site provides additional flexibility and enhances the board’s I/O and processing capabilities, making it ideal for analog I/O and processing. The S5PE-F also features a Board Management Controller (BMC) for advanced system monitoring, which simplifies platform management.

The S5PE-F features a very flexible memory configuration, with two SODIMM sites that support DDR3 SDRAM, RLDRAM3, and QDRII+. Memory card options include the following: up to 8 GBytes of DDR3 with optional error-correcting codes (ECC); up to 36 MBytes QDRII+ (2 banks x18); or up to 512 MBytes RLDRAM3 (2 banks x18). The board also provides Flash memory for storing multiple FPGA images.

 

FPGA

• Intel Stratix® V GX/GS FPGA
• 32 full-duplex, high-performance, multi-gigabit SerDes transceivers @ up to 14.1 Gbps
• Up to 952,000 logic elements (LEs) available
• Up to 62 Mb of embedded memory
• 1.4 Gbps LVDS performance
• Up to 3,926 18×18 variable-precision multipliers
• Embedded HardCopy Blocks

Memory

• 2 SODIMM sites supporting DDR3, RLDRAM3, or QDRII+
• Up to 256 MBytes of Flash memory for booting PGA

PCIe Interface

• x8 Gen1, Gen2, Gen3 direct to FPGA

I/O and Debug Connectors

• Serial ATA: 4 connectors direct to FPGA, 6 Gbps
• Timestamp header: 1 PPS input, reference clock input, and RS-232
• USB 2.0: for debug and programming FPGA and Flash
• Debug Utility header: RS-232 and JTAG to Stratix V

Expansion Site

• 10x high-performance SerDes
• General-purpose I/O

Board Management Controller

• Voltage, current, temperature monitoring
• Power sequencing and reset
• Field upgrades
• FPGA configuration and control
• Clock configuration
• I2C bus access
• USB 2.0 and JTAG access
• Voltage overrides

Size

• Full-length, standard-height PCIe slot card
• x16 mechanical, x8 electrical
• 312mm x 111.15mm
• Max. component height: 14.47mm (single slot), 34.79mm (dual slot)

There are a number of different configurations available. Please contact Sarsen Technology to discuss the options.