Products

The high-performance, power- and cost-efficient Arria V GZ FPGA provides a high level of system integration and flexibility for I/O, routing, and processing. Up to 8 GBytes of on-board memory includes DDR3, QDRII/II+, or RLDRAM3. Two front-panel SFP+ cages allow two 10GigE interfaces.

The A5PS provides a variety of interfaces for high-speed serial I/O as well as debug support. Two SFP+ cages are available on the front panel, each supporting a 10GigE channel using optical transceivers as well as passive copper cabling up to 8 metres.

The Gen3 x8 PCIe interface provides 8 SerDes lanes to the Arria V GZ FPGA. A USB 2.0 interface and an optional JTAG connector are available for debug and programming support. The A5PS also features a Board Management Controller (BMC) for advanced system monitoring, which greatly simplifies platform management.

The A5PS features an extremely flexible memory configuration, with a SODIMM site that supports DDR3 SDRAM, RLDRAM3, and QDRII+. Memory card options include the following: up to 8 GBytes of DDR3 with optional error-correcting codes (ECC); up to 36 MBytes QDRII+ (2 banks x18); or up to 512 MBytes RLDRAM3 (2 banks x18). Additional on-board memory includes flash memory for storing multiple FPGA images. An on-board PROM provides access to the board’s MAC ID.

FPGA

• Intel Arria® V GZ FPGA
• Up to 16 full-duplex, high-performance, multi-gigabit SerDes transceivers @ up to 12.5 GHz
• Up to 450K logic elements available
• Up to 34 Mb of embedded memory
• 1.6 Gbps LVDS performance
• Up to 2278 18×18 multipliers

On-Board Memory

• Flash memory for booting FPGA

Optional SODIMM

• DDR3: x72 w/ECC
  • Up to 8 GB
• RLDRAM3: 2x banks of x18
  • 2x (32 M x 18): 128 MB
  • 2x (64 M x 18): 256 MB
  • 2x (128 M x 18): 512 MB
• QDRII+: 2x banks of x18
  • 2x (8 M x 18): 36 MB

PCIe Interface

• x8 Gen1, Gen2, Gen3 direct to FPGA

USB Header

• USB 2.0 interface for debug and programming FPGA and Flash

Timestamp and Synchronization (Optional)

• Tunable high-accuracy TCXO
• Programmable clock synthesizer (Si5338)

• 2 front panel SMA connectors*
  • 1 PPS input
  • Reference clock input

SFP+ Cages

• 2 SFP+ cages on front panel connected to FPGA via 2 SerDes
• Each supports 10GigE

Baseboard Management Controller

• Voltage, current, temperature monitoring
• Power sequencing and reset
• Field upgrades
• FPGA configuration and control
• Clock configuration
• I2C bus access
• USB 2.0 access
• Voltage overrides

Size

• Half-height, half-length (low profile) PCIe slot card