Products

The S5PH-Q FPGA PCIe board provides a variety of interfaces for high-speed serial I/O as well as debug support. Two QSFP+ cages are available on the front panel, each supporting 40GigE or four 10GigE channels. The QSFP+ SerDes channels are connected directly to the Stratix V FPGA, thus removing the latency of external PHYs. The QSFP+ cages can optionally be adapted for SFP+.

Two SerDes lanes are available via two SATA connectors to connect external storage devices or provide direct board-to-board communication. The x8 PCIe interface provides 8 SerDes lanes to the Stratix V FPGA. USB 2.0, RS-232, and JTAG interfaces are available for debug and programming support. The board also supports timestamping with provision for a 1 PPS and reference clock input as well as RS-232 for connection to GPS or other time sources.

The S5PH-Q also features a Board Management Controller (BMC) for advanced system monitoring, which greatly simplifies platform management.

Several on-board memory banks are available to the Stratix V FPGA. Memory includes up to 16 GBytes of DDR3 SDRAM (two 64-bit banks) and up to 72 MBytes QDRII/II+ (four 18-bit banks). The S5PH-Q also provides flash memory for storing multiple FPGA images.

FPGA

• Intel Stratix V GX/GS FPGA
• 20 full-duplex, high-performance, multi-gigabit SerDes transceivers @ up to 14.1 GHz
• Up to 952,000 logic elements (LEs) available
• Up to 62 Mb of embedded memory
• 1.4 Gbps LVDS performance
• Up to 3,926 18×18 variable-precision multipliers
• Embedded HardCopy Blocks

Memory

• Two banks of up to 8 GBytes DDR3 SDRAM (x64)
• Four banks of up to 18 MBytes QDRII+ (x18)
• 128 MBytes of Flash memory for booting FPGA

PCIe Interface

• x8 Gen1, Gen2, Gen3 direct to FPGA

USB Header

• USB 2.0 interface for debug and programming FPGA and Flash

Timestamp Header

• 1 PPS input
• Reference clock input
• RS-232

Debug Utility Header

• RS-232 port to Stratix V
• JTAG debug interface to Stratix V

QSFP+ Cages

• 2 QSFP+ cages on front panel connected directly to FPGA via 8 SerDes (no external PHY)
• Each supports 40 GigE or four 10 GigE interfaces
• Can be optionally adapted for use as SFP+

Serial ATA

• 2 SATA connectors, connected to FPGA