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XUSP3S


Overview

Xilinx UltraScale 3/4-Length PCIe Board with Quad QSFP, DDR4, QDR-IV, and QDR-II+

The XUSP3S from BittWare is a 3/4-length PCIe x8 card based on the Xilinx Virtex or Kintex UltraScale FPGA.

The board offers flexible memory configurations supporting up to 64 GBytes of memory, sophisticated clocking and timing options, and four front panel QSFP cages, each supporting up to 100 Gbps (4×25) – including 100GigE.

The XUSP3S is ideal for a wide range of data centre applications, including network processing and security, acceleration, storage, broadcast, and SigInt.

Technical

  • Xilinx Virtex UltraScale 80/95/125/160/190 or Kintex UltraScale 115
  • Board Management Controller for Intelligent Platform Management
  • Four QSFP28 cages for 1x 400GigE, 4x 100GigE, 4x 40GigE, 16x 25GigE, or 16x 10GigE
  • Timestamping support
  • • Memory options:
    • up to 64 GBytes of DDR4 SDRAM with ECC
    • up to 36 MBytes QDR-IV
    • Up to 144 MBytes QDR-II+
  • Up to four PCIe x8 interfaces supporting Gen1, Gen2, or Gen3
  • Utility I/O: USB 2.0, serial expansion interface

Specifications

Board Specifications
 
FPGA
  • Xilinx UltraScale FPGA
    • Virtex UltraScale 80/95/125/160/190
    • Kintex UltraScale 115
  • Multi-gigabit transceivers
    • Virtex: 16x GTY at 32.75 Gbps and 32x GTH at 16 Gbps
    • Kintex: 48x GTH at 16 Gbps
  • Up to 1.9 million logic elements
  • Up to 132 Mb of embedded memory
  • Up to 4 integrated PCIe cores
  • Up to 5,520 (Kintex) or 1,800 (Virtex) DSP slices with 27x18 multipliers
 
On-Board Memory
  • Two banks of up to 16 GB DDR4 (x72)
  • Flash memory for booting FPGA
 
Optional SODIMM Memory
  • DDR4: x72 w/ECC - Up to 16 GBytes per SODIMM
  •  
  • QDR-IV: x18 or x36 - Up to 18 MBytes per SODIMM
  •  
  • QDR-II+ x18 - Up to 72 MBytes per SODIMM
 
PCIe Interface
  • Two x8 Gen1, Gen2, Gen3 interfaces direct to FPGA (One x8 interface in a standard slot; two x8 interfaces requires bifurcated slot)
  • Serial Expansion Port can be used for additional two x8 interfaces
 
USB Header
  • Micro USB port (USB 2.0) for debug and programming FPGA and Flash
 
QSFP Cages
  • 4 QSFP28 (zQSFP) cages on front panel connected directly to FPGA via 16 GTY transceivers (GTH for Kintex)
  • Each supports 100GbE, 40GbE, 4x 25GbE, or 4x 10GbE (100GbE, 25 GbE Virtex only) and can be combined for 400GbE
  • Backward compatible with QSFP and can be optionally adapted for use as SFP+
 
Serial Expansion Port
  • Expansion interface to FPGA via 16x GTH transceivers (optional; requires second slot)
 
Timestamping
  • 1 PPS input
  • Reference clock input
Board Management Controller
  • Voltage, current, temperature monitoring
  • Power sequencing and reset
  • Field upgrades
  • FPGA configuration and control
  • Clock configuration
  • I2C bus access
  • USB 2.0 and JTAG access
  • Voltage overrides
 
Size
  • 3/4-length, standard-height PCIe slot card
  • 241mm x 111.15mm
  • Max. component height: 14.47mm single slot, 34.79mm dual slot
 
Development Tools
 
System Development
  • BittWorks II Toolkit - host, command, and debug tools for BittWare hardware; Matlab API; source code porting kit also available
 
FPGA Development
  • FPGA Development Kit
    • Physical interface components
    • Board, I/O, and timing constraints
    • Example projects
    • Software components and drivers
  • Xilinx Tools
    • Vivado® Design Suite
    • Embedded USB to JTAG converter

Technical documents

Ordering information

Contact Sarsen Technology for more information.

Software

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