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The S5PE-DS provides a variety of interfaces for high-speed serial I/O as well as debug support. Four QSFP+ cages are available on the front panel, each supporting 40GigE, 4 10GigE channels, or QDR/FDR InfiniBand. The QSFP+ SerDes channels are connected directly to the Stratix V FPGAs, thus removing the latency of external PHYs.

Eight SATA connectors are provided to connect external storage devices with the FPGAs via SerDes lanes. The Gen3 x16 PCIe interface is supported by a PCIe switch (PLX PEX8733), which provides on-chip DMA engines as well as a Gen3 x8 connection to each FPGA. USB 2.0, RS-232, and JTAG interfaces are available for debug and programming support. The board also supports timestamping with provision for a 1 PPS and reference clock input as well as RS-232 for connection to GPS or other time sources.

The S5PE-DS features an extremely flexible memory configuration, with 8 SODIMM sites (4 per FPGA) supporting DDR3 SDRAM, RLDRAM3, and QDRII+*. SODIMMs are available in the following configurations: up to 8 GBytes DDR3 with optional error-correcting codes (ECC); up to 36 MBytes QDRII+ (2 banks x18); or up to 512 MBytes RLDRAM3 (2 banks x18). The board also provides Flash memory for storing multiple FPGA images.

FPGAs

• 2 Intel Stratix V GX/GS FPGAs
• 28 full-duplex, high-performance, multi-gigabit SerDes transceivers @ up to 14.1 Gbps (per FPGA)
• Up to 952,000 logic elements (LEs) per FPGA
• Up to 62 Mb of embedded memory per FPGA
• 1.4 Gbps LVDS performance
• Up to 3,926 18×18 variable-precision multipliers per FPGA
• Embedded HardCopy Blocks

Memory

• 4 SODIMM sites per FPGA: DDR3 SDRAM, RLDRAM3, or QDRII+ options
• 256 MBytes of Flash memory for booting FPGA

PCIe Interface

• PLX PEX8733 PCIe switch with on-chip DMA engines
• x16 Gen1, Gen2, Gen3 to host
• x8 Gen 1, Gen2, Gen 3 to each FPGA

USB Header

• USB 2.0 interface for debug and programming FPGAs and Flash

Timestamp Header

• 1 PPS input
• Reference clock input
• RS-232

Debug Utility Header

• RS-232 port to Stratix V
• JTAG debug interface to Stratix V

QSFP+ Cages

• 4 QSFP+ cages on front panel connected directly to FPGAs via 16 SerDes (no external PHY)
• Each QSFP+ supports 40GigE, 4 10GigE, or QDR/FDR InfiniBand interfaces

Serial ATA

• 8 SATA connectors, connected to FPGAs

Board Management Controller

• Voltage, current, temperature monitoring
• Power sequencing and reset
• Field upgrades
• FPGA configuration and control
• Clock configuration
• I2C bus access
• USB 2.0 and JTAG access
• Voltage overrides

Size

• Full-length, standard-height, dual-slot PCIe x16 card
• 312mm x 111.15mm
• Max. component height: 34mm